This application is based on Japanese Patent Application 2002-008742, filed on Jan. 17, 2002, the entire contents of which are incorporated herein by reference.
A) Field of the Invention
This invention relates to a manufacturing method of a semiconductor device and a semiconductor chip, more specifically, a semiconductor device and a semiconductor chip using a semiconductor on insulator (SOI) substrate and being capable of improving device property.
B) Description of the Related Art
A technique for improving carrier mobility and controlling short-channel effect by parallelizing a moving direction of carrier of a p-channel MOSFET to a  less than 100 greater than  direction of single crystal silicon is reported (IEDM1999, 27-5, Effect of  less than 100 greater than  Direction for High Performance SCE Immune pMOSFET with Less Than 0.15mm Gate Length).
Also, research and development of a technique for applying an SOI substrate to a semiconductor integrated circuit device have been carried out for more than 20 years. Conventionally, the SOI substrate has been limited to be used in a semiconductor device for a special purpose such as high withstand voltage. Since International Business Machines Corporation adapted the SOI substrate to a microprocessor unit (MPU) in 1998, cases of adapting the SOI substrate to the semiconductor integrated circuit has been increased. When the SOI substrate is used, comprising to that of using a normal semiconductor substrate, it is possible to increase an operating speed of a semiconductor device and lower amounts of electric power consumption.
Conventionally, in a semiconductor integrated circuit device using a silicon substrate, a gate electrode and wirings of the MOSFET were configured to be parallel to a  less than 110 greater than  direction of the silicon substrate. Scribe lines were also configured to be parallel to the  less than 110 greater than  direction; therefore, the substrate could be easily split into chips by cleaving the substrate. Also, since a cleaving direction and a direction to which the gate electrode and the wirings could be observed by cleaving and defection analysis etc. could be performed.
However, when the MOSFET is configured to have the moving direction of the carrier be parallel to the  less than 100 greater than  direction in order to increase the mobility of the extending direction of the gate electrode and the  less than 110 greater than  direction cross at 45-degree angle. For this reason, it is difficult to apart into chips by cleaving. Further, it is difficult to observe the cross section of the gate electrode and the wiring.
It is an object of the present invention to provide a manufacturing method of a semiconductor device that can easily be split into chips even if a moving direction of carrier and a direction to which a wiring extends are shifted from a direction of a crystallographic axis that can be easily cleaved.
It is another object of the present invention to provide a semiconductor chip that is appropriate for applying the above manufacturing method.
According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of: (a) forming a laminated substrate by laminating a device formation layer consisting of single crystalline semiconductor on a supporting substrate consisting of single crystalline semiconductor via an insulating layer wherein a direction of a crystallographic axis of the device formation layer is shifted from a corresponding crystallographic axis of the supporting substrate; (b) forming semiconductor devices on the device formation layer within a plurality of areas divided by scribe lines extending to a direction being parallel to a direction of a crystallographic axis where the supporting substrate is easy to be cleaved; and (c) splitting the laminated substrate into a plurality of chips by cleaving the supporting substrate along the scribe lines.
According to another aspect of the present invention, there is provided a semiconductor chip, comprising: a SOI substrate wherein a supporting substrate consisting of single crystalline semiconductor, an insulating layer and a device formation layer consisting of single crystalline semiconductor are laminated sequentially, and one direction of a crystallographic axis of the device formation layer is shifted from a corresponding direction of a crystallographic axis of the supporting substrate, comprising an end surface parallel to a direction of a crystallographic axis where the supporting substrate is easy to be cleaved; and a semiconductor device formed in the device formation layer.
The laminated substrate can be split into a plurality of chips by cleaving the support substrate because the scribe lines are parallel to the crystallographic axis where the supporting substrate is easy to be cleaved. The crystallographic axis of the device formation layer is out of alignment relative to those of the support substrate. For example, the crystallographic axis can be aligned so as to improve the property of the semiconductor device on the device formation layer.
According to further another aspect of the present invention, there is provided a semiconductor chip, comprising: a SOI substrate wherein a supporting substrate consisting of single crystalline semiconductor, an insulating layer and a device formation layer consisting of single crystalline semiconductor are laminated sequentially, and one direction of a crystallographic axis of the device formation layer is shifted from a corresponding direction of a crystallographic axis of the supporting substrate, comprising an end surface parallel to a direction of a crystallographic axis where the supporting substrate is easy to be cleaved; and an active device formed in the device formation layer, a moving direction of carrier of active device being the  less than 100 greater than  direction of the device formation layer.
The carrier mobility can be increased by making the moving direction of carriers parallel to  less than 100 greater than  direction.
According to yet further another aspect of the present invention, there is provided a semiconductor chip, comprising: a SOI substrate wherein a supporting substrate consisting of single crystalline semiconductor, an insulating layer and a device formation layer consisting of single crystalline semiconductor are laminated sequentially, and one direction of a crystallographic axis of the device formation layer is shifted from a corresponding direction of a crystallographic axis of the supporting substrate, comprising an end surface parallel to a direction of a crystallographic axis where the supporting substrate is easy to be cleaved; a semiconductor device formed in the device formation layer; and a wiring layer comprising a plurality of wirings substantially extending to one direction wherein the plurality of wirings in the wiring layer and the direction of a crystallographic axis where the supporting substrate is easy to be cleaved are configured to be substantially parallel.
The section of the wiring can be observed and analyzed by cleaving the support substrate.
As described above, the directions of the crystallographic axis of the supporting substrate and the device formation layer are shifted each other. The direction of the crystallographic axis of the device formation layer is appropriated to improve the property of the semiconductor device, and the direction of the crystallographic axis of the supporting substrate is appropriated to easily be split into chips by cleaving.